This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2001-394884, filed on Dec. 26, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor design/fabrication system, a semiconductor design/fabrication method and a semiconductor design/fabrication program which selects arbitrary function blocks from a plurality of function blocks and arranges the selected function blocks on a chip.
2. Related Background Art
It takes too much time and cost to develop an LSI chip from scratch. Because of this, design method in which desirable function blocks are selected if necessary from a plurality of function blocks that operational verification has already been done, and the selected function blocks are arranged on the chip, is generally adopted.
Request for the chips is vary by each user. For example, one user requests chip cost reduction, the other user requests short delivery time even if cost is somewhat high, or the other user requests reduction of defective rate.
Even when the function blocks are combined and arranged on the chip, an yield and a fabrication cost are largely affected by the types of the selected function blocks and how to arrange the function blocks.
However, the method of selecting the optimum combination of the function blocks in accordance with user""s request has not been conventionally established. Because of this, user had to combine the function blocks by cut and try, and arrange the combined function blocks on the chip to verify them. Accordingly, there was a problem in which it takes time to find the optimum combination of the function blocks.
A semiconductor design/fabrication system according to one embodiment of the present invention which combines a plurality of function blocks and arranges the combined function blocks on a chip, comprising:
a function block selector which selects the function blocks to be arranged on the same chip from a plurality of function blocks for each of which a critical area indicating a range where defective products occur due to existence of defects is known;
a chip information calculator which calculates a sum of said critical areas on each of the selected function blocks;
an yield calculator which calculates an yield based on a calculation result of said chip information calculator and defect occurrence rate information of a chip fabrication line;
a cost delivery time information calculator which calculates information relating to fabrication cost and delivery time of the chip based on a calculation result of said yield calculator and fabrication management information relating to cost and fabrication period of the chip fabrication line; and
a combination selector which selects a combination of the function blocks constituting the chip based on the information relating to the fabrication cost and the delivery time of the chip calculated by said cost delivery time information calculator.